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> Nand Structure, layout structure of NAND
abm_y4k
post Dec 14 2007, 02:47 AM
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Hi all,

Can someone help me out on understanding the layout struture of the NAND in C3x?

I want to know the starting address and ending address for:

1. kernel
2. uboot


I want to know this since I am trying to flush the new kernel from yonggun but the provided NAND address in autoboot.sh seems not working on my c3100. after running the flush, killed my zaurus....

so besically I want to know the layout of the NAND so I will make sure address correct before I do flushing smile.gif


Thanks all,
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speculatrix
post Dec 14 2007, 04:24 AM
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QUOTE(abm_y4k @ Dec 14 2007, 10:47 AM) *
Can someone help me out on understanding the layout struture of the NAND in C3x?


take a look at recent discussions on the angstrom mailing list as there's been a rewrite of Angstrom's updater.sh tool which has all sorts of stuff in it for managing the mtdblock devices

cacko's install scripts also allow flash repartitioning, so they might be a useful reference point too
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Dromede
post Dec 14 2007, 06:02 AM
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The following text is from luigi600's webpage:

Index
1 Introduction
2 Hardware Overview
3 Flash Partitions
4 A Hypothesys To What Goes On During Boot
5 A Closer Look at The Sharp Boot Loader
6 A Closer Look at The New pdaXrom Boot Loader (u-boot)

1 Introduction

I've found grate difficulty in getting a decent level of detail in the
ZAURUS cxx0 family boot process. There is probably a good deal of information
scattered around on various forums and web sites but this approach is too
dispersive when you want to collect all the pieces of the puzzle to get an
overall view of what is going on at boot time.

So this is just an attempt to put some pieces together along with some
conciderations I made in order to get an overall view of the way cxx0 boots.
I've a pretty poor experience on this hardware so some/all of what I put
togeter along with my conciderations may be totally wrong.
So any experienced people are invited to help me in producing more accurate
and complete documentation on this matter.



2 Hardware Overview

An overview on the hardware specs that are readily avalible form anywhare:
CPU: Intel XScale-PXA255 (400Mhz) {this may be model dependent}
MEM: 64 Mb ram {not sure if all models have the same ram}
8 Mb flash (sharpsl-flash nor)
128 Mb flash (sharpsl-nand)
IO: serial and usb client on the sharp io port connector
sd
cf
audio
irda
VIDEO: ati grafix controller {I opened a c760 and found an ati chip}



3 Flash Partitions

The onboard flash devices (there are 2) are logically partitioned in different
ways according on what's running on the device (main difference being between
sharp derivates and non sharp derivates). Some implementations have the
logic partitions hard coded to kernel source some pass the partitioning scheme
to the kernel via append from the boot loader.

First thing one might notice is that the sum of all the flash device space is
more than 128Mb this is because there is 2 physical flash chips inside.

Now let's see what's in these partitions:

This is how the flash is partitioned on a c760 running pdaxrom1.1.0beta1
/dev/mtdblock0 6976K (0x6d000@0x120000:6976K@1152k)
/dev/mtdblock1 7168K (0x700000@0x0:7168K@0)
/dev/mtdblock2 51200K (0x3200000@0x700000:51200K@7168K)
/dev/mtdblock3 72704K (0x4700000@0x3900000:72704K@58386k)

Actually on a pdaXrom 1.10beta4 there is only 3 partitions (root and home have
been placed all in one jffs2 filesystem).

The first partition (/dev/mtdblock0) is part of the first 8Mb device, that
should only ever be used as read only as it contains vital maintenence data
(like the Fn+D+M menu) and possibly other importatn stuff too.
The firs 1152K appear to be unused but most likely contain the
Primary Boot Loader (sometimes reffered as BL1) as described in the pxa25x
technical documentetion after reset the first instruction executed is
@ physical address 0x0 (which should be the first byte of the sharpsl-flash).
I've not yet found any documentation describing exactly what's on this chip
so what I wrote above is just a hypothesis. Sash has a disassembled source
of what's in there ... I'll update when I get to see it.
The data in mtd0 is regarded as ROM but is physically in a flash so I guess
there is a way of mangling it up (regard is as out of bounds unless you
really know what you're doing).


/dev/mtdblock1 contains the the flash image of the D+M menu and some boot
loader code (most probably the BL2 see,
http://linuxdevices.com/articles/AT2779754250.html for referance) and the
PWR+OK flash menu.
n pdaXrom beta4 or above it contains u-boot image, kernel and rescue system.

/dev/mtdblock2 contains the root filesystem
/dev/mtdblock3 contains the home filesystem

See for referance:
http://externe.net/zaurus/flash/nandmap.jpg (6000 flash layout but bossybly
also applicable to cxx0 devices)

http://www.oesf.org/forums/index.php?showt...-boot&st=45
(for more info on restoring original D+M menu in flash, not the one in readonly
flash that is generally regarded as rom)


4 A Hypothesys To What Goes On During Boot

So here is my hipothesis:
Processor is reset and execution addres register points to physical address
0x0 (that should be in sharpsl-flash). At that address begins the BL1 (or a
jump to where ever that is). This BL1 code must ither be small enough to fit
in the memory arranged area of a nand chip or be placed in a nor flash chip.
(BL1 area refered by http://linuxdevices.com/articles/AT2779754250.html)
This sort of Primary Boot Loader initiates all the mandatory hardware for
boot and then loads some sort of Secondary Boot Loader. As documented in the
above link this may be done a 3 phases:
first the BL1
then some extra code from fixed reagions in a flash device
then the BL2

BL2 is written at the beginning of mtd1 (physically @ offset 0x0 of the 128Mb
nand flash chip). BL2 is responsable for doing the rest of the initialization
required for loading and executing the kernel.

5 A Closer Look at The Sharp Boot Loader

I need help on this.
I did find some intresting things on this forum thread:
http://www.oesf.org/forums/index.php?showt...;hl=nandlogical

Here is a summery of the intresting stuff found there:
Sharp's maintenence kernel is configured (by kernel parameters stored in flash)
only to have 2 partitions. The intresting thing is that the flash area
containing this info can be patched (if you do this make sure you have a full
nand backup you can restore).
The information is stored in /dev/mtd1 but the exact location may be model
dependent. On this ara of the flash you should allways use nandlogical bacause
of a wear leveling feature introduced by sharp.

The example below is relevent to a c760, on other models exact locations may
vary.

To read the partitioning scheme:
nandlogical /dev/mtd1 READ 0x209F4 80 mtdparts

The content should be something like this:
%d mtdparts=sharpsl-nand:7168k@0k(smf),k@7168k(root),-(home) ZAURUS_RESE

You can edit it and rewrite the modified version back to flash.
You might like to copy the mtdparts file to mtdparts_tweaked and modify it to
something like this:
d mtdparts=sharpsl-nand:7168k@0k(smf),-(root)root),-(home) ZAURUS_RESE
Then you could rewrite the modified version into the flash like this:
nandlogical /dev/mtd1 WRITE 0x209F4 80 mtdparts_tweaked



6 A Closer Look at The New pdaXrom Boot Loader (u-boot)

Sash did some grate work on the u-boot for pdaXrom and there is some
documentation on his work in the "related projects" at this url:
http://mail.pdaxrom.org/node/89
but he left the u-boot project fro pdaXrom in a working but not finished state.
I mean it's working fine but only a very small portion of what could be
obtained has actually been implemented. I'm currently looking at u-boot-1.2
to see if I can get any more features working ... but I'm a terrible programmer
so do not expect anything.

Anyway I took some of the documentation from http://mail.pdaxrom.org/node/89
and attempted to make it more readable for non experienced people like me ;-)

What follows is a log from the serial console while booting with u-boot while
it was still in an experimental stage. You can notice the old (sharp like)
partition scheme and u-boot split up in code and env.

U-Boot 1.1.4 (May 21 2006 - 17:28:48)

DRAM: 64 MB
NAND:128 MiB
In: serial
Out: serial
Err: serial
Hit any key to stop autoboot: 0
U-Boot> nand info

Device 0: NAND 128MiB 3,3V 8-bit, sector size 16 KiB
U-Boot> mtdparts

device nand0 <laze-0>, # parts = 5
#: name size offset mask_flags
0: U-Boot 0x00040000 0x00000000 1
1: U-BootEnv 0x00020000 0x00040000 0
2: Emergency 0x00540000 0x00060000 0
3: Kernel 0x00160000 0x005a0000 0
4: JFFS2 0x07900000 0x00700000 0


active partition: nand0,0 - (U-Boot) 0x00040000 @ 0x00000000

defaults:
mtdids : nand0=laze-0
mtdparts: mtdparts=laze-0:256k(U-Boot)ro,128k(U-BootEnv),5376k(Emergency),1408k(Kernel),-(JFFS2)
U-Boot> printenv
bootargs=console=ttyS0,115200 console=tty1 root=/dev/ram rw ramdisk_size=8192
bootcmd=if testkey 101 ; then nand read 0xa1000000 0x00060000 0x00540000; setenv bootargs console=ttyS0,115200 console=tty1 ri
bootdelay=1
baudrate=115200
mtdids=nand0=laze-0
mtdparts=mtdparts=laze-0:256k(U-Boot)ro,128k(U-BootEnv),5376k(Emergency),1408k(Kernel),-(JFFS2)
stdin=serial
stdout=serial
stderr=serial
partition=nand0,0
mtddevnum=0
mtddevname=U-Boot

Environment size: 625/131068 bytes
U-Boot>
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abm_y4k
post Dec 14 2007, 09:42 AM
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got some info on uboot wink.gif

I just wonder for zimage.bin the starting address seems to be at 0xe0000:

this line I found in many distributions:
/sbin/nandlogical $LOGOCAL_MTD WRITE 0xe0000 $DATASIZE $TARGETFILE > /dev/null 2>&1

whereas the kernel.img yonggun mentioned by zdevil use a different address:

nandlogical /dev/mtd1 WRITE 0x5a0000 0x160000 $DATAPATH/$TARGETFILE

so I am confused over the different btw kernel.img and zimage.bin.. aren't they same?

I also noticed that the address with 0xe0000 is without uboot, and 0x5a0000 is with uboot.
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CoreDump
post Dec 25 2007, 07:46 AM
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QUOTE(abm_y4k @ Dec 14 2007, 06:42 PM) *
got some info on uboot wink.gif

I just wonder for zimage.bin the starting address seems to be at 0xe0000:


For SHARP bootloaders on SL-Cxx00, yes.

QUOTE
this line I found in many distributions:
/sbin/nandlogical $LOGOCAL_MTD WRITE 0xe0000 $DATASIZE $TARGETFILE > /dev/null 2>&1

whereas the kernel.img yonggun mentioned by zdevil use a different address:

nandlogical /dev/mtd1 WRITE 0x5a0000 0x160000 $DATAPATH/$TARGETFILE

so I am confused over the different btw kernel.img and zimage.bin.. aren't they same?

I also noticed that the address with 0xe0000 is without uboot, and 0x5a0000 is with uboot.


Exactly, the pdaXrom u-boot installation uses a different address for the kernel (0x5a0000) and also allows for
a bigger zImage (~1,2Mb SHARP vs ~1.4Mb pdaXrom).
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