What you say here about the EMI contradicts what has been said earlier
if it stalls the SDRAM then it must share the SDRAM adress and data pins if so then i will avoid it as it is WAY to slow
i still dont think everyone is on the same page. it seems that some points have already been adressed in other posts that people have not read or do not understand. i will clean up the wiki and post the overview here to clear it up. we are getting to much fragmentation here
as for the CF vs ATA, think 16MB/s vs 66MB/s with DMA acsess. (not that that really means anything) and also think shared bus vs dedicated bus. keeping in mind that the CF card might not reach that speed and those are theroaticl maximums
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It's all in the nature of the transactions. Only the Address pins are multiplexed between WEIM and SDRAM, and because of the burst nature of the transactions they will not interfere too much with each other. Because each is actually attached to a different arbiter it is my understanding that these transactions can overlap, in that one can start before the other finishes. Even within the same arbiter they can and will overlap, being held until a slot is ready. Now the WEIM flash interface because it is fast, and because it is on a different path ( ie internal bus in the memory interface ) will not slow down the SDRAM access to any noticable degree. When DMA is underway for the graphics subsystem, then the WEIM will rarely "interfere" with these transactions because of the overlapping or interleaved transactions. With the PCMCIA things are totally different, in that a transaction can be slow, very slow, and held off by the PCMCIA card ( or CF card ) using the control pins. From my reading of the datasheets, this "beat" of a transaction will not be split or aborted, and thus will cause overall system degredation. To a lesser extent ( much lesser ) the NAND interface suffers the same problem. It can have relatively slow transactions, but when a single "beat" of a transaction is complete the arbiter will throw it off the bus if something else comes along. The request from the SDRAM controller is cascaded down to the peripheral arbiter, and so will take highest priority.
The address phase of each burst transaction is a small percentage of the total transaction time that it should not impact noticeably on the other arbiter.
The NAND controller decouples from the SDRAM bus by using the NAND IO bus, which is comparitively slow when put against the WEIM, not particulary efficient, but is easier to hook up.
Again all this is moot in that if you are only using the flash to boot then it is as good to put it on NAND controller. It will be a little slower to boot and launch off of, but I doubt anyone would notice.
I think you are getting hung up on the shared/dedicated bus thing. The NAND bus will always be slower than the WEIM. The SDRAM will barely be slowed by the WEIM, and the flash on the WEIM will produce a faster system. As you do not intend to run from flash then it doesn't matter. If you intend to load apps from flash, then again I would consider the WEIM.
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