I'm Disappointed

[Ragnorok]

...[snip]...12 cpu machine with each core at 733Mhz that can each address up to 2GB of ram each the design of the CPU is much cleaner, for example each instruction is conditional not just branches allowing you to do a
if x !=0
{
x++
}
in one instruction, dosent mean much to you guys but lets just say that it can give you a very nice speed boost.
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- Man, Da_Blitz, you are just out there!  I'm jealous!  (wolfish grin)  I kinda migrated away from a very strong hardware background somewhere over 15 years ago ... coincidentally at exactly the same time that I started programming for a living.  Will wonders never cease?
- 12 CPUs in 80 watts.  Nice!  Monsterous speed in a monstrous package!  (wink)  Talk about "luggable".  (heh heh)  'Course a first-rate fab plant could probably put that on a 50mm die without a lot of effort.  Now if I could just find where I put that darned thing!
- This instruction example reminds me of ENIAC ... it had ten ALU/register combo units, and each one *had* to do an arithmetic operation every time, so they'd add zero if something was being done that they didn't want the number to change.  (snicker)  Off-topic ... sorry!
- Does the cross-compiler for the Z generate the approriate instructions to take advantage of this compact execution, or does cross-compiled code lose that?  Or is that just the high-end Xscale?  Or does the Z use something different and I've skipped a groove again??  (drool)...

[Da_Blitz]

the stuff i was talking about was arm apecific, not xscale  however i am not sure if gcc can optimise to that level

what i like about the xscales is they sacrificed some power saving tradeoffs for raw speed, word on the net is that the other arm manufactures arent happy with this which is the reasong behind the arm11 chips, arm tried to release a chip to stay competitive with intel.

some other cool stuff from the arm chips is the 16 registers that can also act as index registers or even the PC if you wanted, in fact R16 is the PC which allows you to add 16 to R16 and jump ahead 16 instructions!

what intel has really done is polish the entire ARM packeage by adding insane amounts of cache compared to the standard chip and heavy pipling to bump up the clock speeds. in fact intel even tests the low power tech on the xscales before it goes in the P4's and as far as i know the xscales are the only ARm chips manufactured at 90nm

the iwmmx is nice as well, all the mmx instructions AND the integer sse ones as well (not sure how many there were thogh)

not sure about the optimisation, dont think so but am currently trying to find out. i belive its because the gcc toolchain is so closly aligned with the x86 arch that they might not think of somthing like this, however i might be wrong

hopefully i should get the cpus' up some time next year, but if you are looking for real power there is another intel chip thats been doing the CELL mini cpu thing for a couple of years now, its a 1.1Ghz xscale core with 4 900mhz mini cpus and supports up to 12GB of RAM in total and PCI-e see: http://www.intel.com/design/network/produc...ily/ixp2350.htm

i will have to look into the ENIAC chip, was it a VLIW cpu?

ive gone off topic already if you want more info email me

[lardman]

Not sure this is all that off-topic -> the topic title is fairly broad.

Please continue, I'm interested


Si

[Da_Blitz]

i normally sum it up at this point by saying "Xscales kick some serious arse" i really dont think there is much more to say at this point, any questions that anyone wants ansered.

one thing i might clarify is if you have read my posts about CF cards and RAM and why they are bad for each other, the best way to sum it up is they want the same hardware and they fight for it, unfortunattly the odds are 50:50 even worse is that CF is slow and kill performance. you are better off with USB of SD, if you are watching moives i would only do it off SD or USB due to the performance hit.

[Ragnorok]

the stuff i was talking about was arm apecific, not xscale :) however i am not sure if gcc can optimise to that level

- So I did skip a groove.  Just not the one I imagined.  (snicker)  Typical.

...[snip]...
not sure about the optimisation, dont think so but am currently trying to find out. i belive its because the gcc toolchain is so closly aligned with the x86 arch that they might not think of somthing like this, however i might be wrong

- Not surprising.  The surprising thing was that gcc would work for Z compilation at all.  At least to me.  Any compiler in a storm, no?

hopefully i should get the cpus' up some time next year, but if you are looking for real power there is another intel chip thats been doing the CELL mini cpu thing for a couple of years now, its a 1.1Ghz xscale core with 4 900mhz mini cpus and supports up to 12GB of RAM in total and PCI-e see: http://www.intel.com/design/network/produc...ily/ixp2350.htm

- Sweet!  Seems a bit specific to network processing, but that gives it some interesting capability, like four built-in ethernet ports.  (snicker)  Didn't delve too deeply to see if that's an issue or not, or what it's power requirements are.

i will have to look into the ENIAC chip, was it a VLIW cpu?

ive gone off topic already if you want more info email me
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- (guffaw)  ENIAC is credited as being the first "programmable" electronic computer ever built, circa 1949.  It was comprised of over 18,000 tubes, filled a large room, consumed megawatts of power, and ran an average of thirty seconds between crashes, operating at a phenomenal rate of 3500 instructions per second.  I found a book published in 1956 that completely describes ENIAC's design and operation.  Very interesting, from an historical perspective.

- Now where did that topic go?  It was just right here.  Oh yeah.  How's that for a sorry state of computing?  Makes me happy to see what's available now.  (cheshire grin)