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ranma
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Joined: 13-October 07
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Last Seen: 5th July 2009 - 09:17 AM
Local Time: Jun 19 2013, 05:13 AM
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15 Jun 2008
Hi all!
I recently looked into how the NAND is hooked up on the Zaurus (my C750): CODE TP6 TP5 TP4 --------- TP3 |Xilinx | TP2 |CPLD | TP1 | | --------- TP1 => CE0 TP2 => CE1! (unused?) TP3 => /WP TP4 => /WE TP5 => ALE TP6 => CLE I also found two nicely compatible 8GBit TSOP48 Toshiba Flash Chips in a CNMemory 2GByte CF Card. So I soldered one of the 8GBit chips on top of the already existing 512MBit chip (all signals except CE are shared). Soldering was a bitch though (pins did almost, but not quite reach the pins below), but with lots of solder, cursing, solderwick and patience I eventually had all relevant pins connected. Since the Linux kernel unfortunately always enables/disables both CE signals I couldn't simply use the CE1 signal from the CPLD, but for now (first tests) I hooked up CE to the Cathode of the Green EMail-LED (which is normally always off and the transistor acts as an inverter, so 'on' == low, exactly what I need) and a 10k pull-up. The system boots fine and a hacked up 'fiddle with CEs and read IDs' kernel module finds both Chips just fine: CODE Trying to read id from Flash on CE0 Got maker=98 device=76 Trying to read id from Flash on CE1|GreenLED Got maker=98 device=d3 According to drivers/mtd/nand/nand_ids.c maker 0x98 is 'Toshiba', device 0x76 is a 'NAND 64MiB 3,3V 8-bit' and device 0xd3 is the shiny new 'NAND 1GiB 3,3V 8-bit' (Yay!). This should actually already exercise all control signals, so the only remaining task is to modify the built-in sharp_sl nand driver to properly support two chips. |
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Lo-Fi Version | Time is now: 19th June 2013 - 05:13 AM |